In the field of microprocessor architecture, it is known to provide so-called “multi-core” devices. As the name suggests, a multi-core device comprises a number of processor cores, for example two cores. Microprocessors with multiple cores provide a number of benefits. One known benefit is an increase in performance by the additional capacity provided by an additional processor, resulting in a pair of processors operating in an asynchronous manner so that a greater processing workload can be undertaken as compared with a single-core processing device.
Another benefit of multi-core devices, when operating in a synchronous manner, is increased redundancy that can be used to support so-called mission-critical applications, where a backup core is required in order to protect against situations when a primary core can fail. Furthermore, it is becoming desirable to make the multi-core devices switchable between the synchronous and asynchronous modes.
In order to switch between an asynchronous mode and a synchronous mode, a synchronisation step needs to be performed in order to change the states of the processing cores so that the states of the two cores are identical. To achieve synchronisation, the state of a first core has to be copied to a second, redundant, core. In this respect, the first core comprises static Random Access Memory (RAM) and flip-flops, the data stored in the static RAM and the states of the flip flops characterising the state of the first core.
Replication of the contents of the static RAM is a relatively straightforward task. However, copying the states of the flip-flops is not as easy as in respect of the static RAM. Additionally, the number of flip-flops of the first and second cores can be quite large, for example more than 6500 flip-flops each. Consequently, significant additional software or dedicated hardware has to be provided in order to copy the respective states of a first number of flip-flops of the first core to a second set of flip-flops of the second core. Moreover, use of software to copy the states of the flip-flops disadvantageously typically requires at least two thousand, and possibly several thousand, processor cycles. Furthermore, to achieve such synchronisation, the first and second cores have to be reset and software executed to run both cores in a so-called “lock-step” manner. This technique therefore reduces system availability for the performance of critical functions.